The present disclosure relates to a direct current to direct current (DC/DC) converter.
In an electronic machine or system that is supplied with a power supply voltage VCC with a certain voltage level, a buck DC/DC converter is used when the operation voltage of the internal circuit is lower than the power supply voltage VCC.
FIG. 1 is a circuit diagram of a buck DC/DC converter investigated by the present inventors. The DC/DC converter 100r receives the input voltage (power supply voltage) VCC from the input line 102, reduces the input voltage and then stabilizes the reduced voltage to generate an output voltage VOUT having a specific target voltage level, which is supplied to a load (not shown in the drawing) connected with the output line 104.
The DC/DC converter 100r comprises an output circuit 106 and a control integrated circuit (control IC) 200r. The DC/DC converter 100r is a rectifier diode-type converter, and the output circuit 106 comprises a switch transistor M1, a rectifier diode D1, an inductor L1, and an output capacitor C1.
The control IC 200r comprises an input terminal (VCC), a switch terminal (LX terminal), a ground terminal (GND), and a bootstrap terminal (BST). When disposing (integrating) the switch transistor M1 in the control IC 200r, the N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used in order to reduce the size of the circuit. The drain of the switch transistor M1 is connected with the VCC terminal, while the source of the switch transistor M1 is connected with the LX terminal.
The output voltage VOUT is divided by resistors R1 and R2, and fed back to the voltage detection terminal (VOUT) of the control IC 200r via the feedback line 108. The error amplifier 202 amplifies the error between the fed-back detection voltage VS and a specific reference voltage VREF. The duty cycle controller 204 comprises a pulse width modulator or a pulse frequency modulator, or a combination of the two; it generates a pulse signal S1 by modulating the duty cycle ratio as though the error is close to zero. The high-side driver 206 switches on or off the switch transistor M1 according to the pulse signal S1.
In order to conduct the switch transistor M1 for use as the N-channel MOSFET, the high-side driver 206 has to apply to the gate of the switch transistor M1 a driving voltage VH, which is higher than the power supply voltage VCC. A bootstrap circuit is used to generate the driving voltage VH.
The bootstrap circuit comprises a bootstrap capacitor C2, a diode D2, a low-side transistor M2, a low-side driver 208, and an internal adjuster 210. The internal adjuster 210 comprises a linear regulator for receiving the power supply voltage VCC and reducing the voltage of thereof, and generating a stabilized, internal voltage VREG. The diode D2 is disposed between the output terminal of the internal adjuster 210 and the BST terminal. The bootstrap capacitor C2 is disposed between the LX terminal and the BST terminal.
The low-side transistor M2 is disposed between the LX terminal and the GND terminal. The duty cycle controller 204 generates a control signal S2 of the low-side transistor M2 synchronously with the pulse modulation signal S1. The control signal S2 is generated by conducting the low-side transistor M2 during at least a portion of the turn-off period of the switch transistor M1.
When the switch transistor M1 is switched off and the low-side transistor M2 is conducted, the potential of the LX terminal is zero V. At this time, one terminal (the BST terminal) of the bootstrap capacitor C2 is charged by the internal adjuster 210 via the diode D2. The power source terminal at the high side of the high-side driver 206 is supplied with the voltage of the BST terminal.
In this case, in the application where the input power supply voltage VCC is preferably about 48 V at maximum, a high-voltage element capable of handling voltages up to 60 V is used as the switch transistor M1 or the low-side transistor M2; one example of the above-mentioned high-voltage element is a DMOS (Double-Diffused MOSFET) having the double-diffused MOS structure.
FIG. 2 is a cross-sectional view of a semiconductor device 300 having the DMOS structure. An N-type epitaxial layer 302 for use as the semiconductor layer and a P-type isolating diffusion region 303 surrounding the peripheral (lateral) ring of the N-type epitaxial layer 302 and for use as the isolating region are formed on the P-type semiconductor substrate 301. A P-type body diffusion region 304 for use as the body region is formed on the surface layer portion of the N-type epitaxial layer 302. An N-type source diffusion region 305 for use as the source region and a P-type body contact region 306 are also formed on the surface layer portion of the P-type body diffusion region 304. The N-type source diffusion region 305 and the P-type body contact region 306 are connected to the ground. A drain diffusion region 308 for use as the drain region is formed on the surface layer portion of the N-type epitaxial layer 302. An oxide film layer 309 is formed on the gate region at the surface of the N-type epitaxial layer 302; a gate electrode 310(G) is formed on the oxide film layer 309. An N-type embedded diffusion layer 314 is formed at the injunction of the P-type semiconductor substrate 301 and the N-type epitaxial layer 302.
The P-type isolating diffusion region 303 comprises, a low-side isolating diffusion region 311 connected to the lower side of the P-type semiconductor substrate 301 and a high-side isolating diffusion region 312 formed on the low-side isolating diffusion region 311. The high-side isolating diffusion region 312 is connected to the ground, and the potential of the P-type semiconductor substrate 301 is fixed to the grounding voltage (0 V).
Regarding the DMOS for use as the low-side transistor M2, the drain (D) thereof is connected with the LX terminal, while the source (S) thereof is connected with the GND terminal. The periphery of the low-side transistor M2 is surrounded by a guard ring 220 having a vertical N-well structure. The guard ring 220 comprises an N-type embedded diffusion layer 222, a diffusion region 224 disposed on the N-type embedded diffusion layer 222, and a contact region 226. The contact region 226 is fixed to the power supply voltage VCC.